LICENSE
MANIFEST.in
README.md
setup.py
pythondata_cpu_vexriscv/__init__.py
pythondata_cpu_vexriscv.egg-info/PKG-INFO
pythondata_cpu_vexriscv.egg-info/SOURCES.txt
pythondata_cpu_vexriscv.egg-info/dependency_links.txt
pythondata_cpu_vexriscv.egg-info/not-zip-safe
pythondata_cpu_vexriscv.egg-info/top_level.txt
pythondata_cpu_vexriscv/verilog/.gitignore
pythondata_cpu_vexriscv/verilog/.gitmodules
pythondata_cpu_vexriscv/verilog/Makefile
pythondata_cpu_vexriscv/verilog/README.md
pythondata_cpu_vexriscv/verilog/VexRiscv.v
pythondata_cpu_vexriscv/verilog/VexRiscv.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v
pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v
pythondata_cpu_vexriscv/verilog/VexRiscv_Full.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v
pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v
pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v
pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v
pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v
pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v
pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v
pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v
pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v
pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v
pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebugHwBP.v
pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebugHwBP.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v
pythondata_cpu_vexriscv/verilog/VexRiscv_Min.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v
pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebugHwBP.v
pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebugHwBP.yaml
pythondata_cpu_vexriscv/verilog/VexRiscv_Secure.v
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pythondata_cpu_vexriscv/verilog/build.sbt
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/.gitignore
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/.travis.yml
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/LICENSE
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/README.md
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/build.sbt
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pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/spinal/lib/bus/wishbone/Wishbone.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/spinal/lib/eda/icestorm/IcestormFlow.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/spinal/lib/misc/HexTools.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/Pipeline.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/Riscv.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/Services.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/Stage.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/TestsWorkspace.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/VexRiscv.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/Briey.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/CustomCsrDemoPlugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/CustomInstruction.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/FormalSimple.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/GenCustomCsr.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/GenCustomSimdAdd.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/GenDeterministicVex.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/GenFull.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/GenFullNoMmu.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/GenFullNoMmuMaxPerf.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/GenSmallAndPerformantICache.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/GenSmallest.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/Murax.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/MuraxUtiles.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/SimpleBus.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/SynthesisBench.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/ip/DataCache.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/ip/InstructionCache.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/BranchPlugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/CsrPlugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/DebugPlugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/DivPlugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/DummyFencePlugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/ExternalInterruptArrayPlugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/Fetcher.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/FormalPlugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/HaltOnExceptionPlugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/HazardPessimisticPlugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/IntAluPlugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/MemoryTranslatorPlugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/Misc.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/MulPlugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/NoPipeliningPlugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/PcManagerSimplePlugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/Plugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/RegFilePlugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/ShiftPlugins.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/SingleInstructionLimiterPlugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/SrcPlugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/StaticMemoryTranslatorPlugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/plugin/YamlPlugin.scala
pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/test/Swing.scala
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